
module top (
    
);
    reg clk;
    reg nrst;

    wire [7:0] count;

    always #50 clk <= ~clk;
    
    initial begin
        clk = 0;
        nrst = 0;
        #100
        nrst = 1;
    end

    wrap u_wrap(clk, nrst, count);

    always @(posedge clk) begin
        if (nrst) begin
            $display("count: %d\n", count);
        end
    end

endmodule